This invention relates in general to frequency prescalers, and to high-speed prescalers and prescaling methods in particular.
Frequency synthesizers which utilize phase-locked loop (PLL) circuits may be useful in various types of electronic equipment, such as radio-frequency signal generators, test equipment, radio-frequency telecommunications equipment, and lightwave telecommunications equipment. One known method of synthesizing a desired frequency involves dividing the desired frequency by a preselected value in a PLL.
Frequency synthesizers based on PLL circuits which can divide a desired frequency by a range of values are also known. One such frequency synthesizer has a B+N frequency prescaler. A B+N prescaler is a cascaded prescaler that divides a desired frequency by "B" plus "N". Such prescalers may have "noisy" output signals and may have output signals which are insufficient in duration, and cannot achieve a sufficiently low minimum divide value for many applications.
Therefore, there is a need for a prescaler that can be configured to divide over a wide range of values, with a low minimum divide value, low noise, and which provides an easily detected output signal.